SHF: Self-Adaptive Interference-Avoiding Wireless Receiver Hardware through Real-Time Learning-Based Automatic Optimization of Power-Efficient Integrated Circuits
The sheer number of devices in the Internet of Things (IoT) is creating an extremely crowded and dynamic spectrum environment. As such, continuous and seamless adaptation of wireless-communication parameters will become essential in the next few years. On the other hand, typical radio-frequency (RF) integrated circuits are statically optimized for a fixed set of parameters and communication standards, which leaves limited room for real-time optimization at the intersection of hardware and software. Indeed, many of today’s devices are tailored for worst-case scenarios associated with a particular communication standard, which leads to limited performance and excessive power consumption. Conversely, real-time optimization allows to quickly reconfigure circuits for energy-efficient operation while achieving system-level performance goals. This challenge will be addressed by devising Radio Real-Time Machine Learning (RadioRTML), a platform that will demonstrate the feasibility of automatic RF integrated-circuit optimization through machine learning (ML) techniques directly implemented with reconfigurable hardware. This research will transform how the optimization of radio frequency systems is done today by demonstrating that real-time ML-based adaptation of RF parameters is able to achieve significant performance improvements. The outcomes will have long-lasting benefits for the design and optimization of low-power RF circuits for adaptive energy-efficient communication. Furthermore, the project will provide unique training for graduate and undergraduate students at the crossroads of machine learning and integrated circuit design.
Automatic machine-learning-based optimization of RF integrated circuits will be investigated through digital control of analog RF front-end circuits. Novel deep reinforcement-learning (DRL) algorithms will be developed to deliver unprecedented flexibility while improving energy efficiency and minimizing interference impacts. A key challenge in the application of DRL is to design a policy network expressive enough to achieve the required performance, yet implementable in a resource-constrained embedded IoT platform. For this reason, new techniques for effective and efficient policy network design will be created. Since DRL is known to exhibit slow convergence times and high energy consumption, this research will include the design of novel transfer-learning techniques to speed up DRL convergence, and it will leverage edge-computing techniques to significantly reduce the energy consumption of the platform. At the RF circuit level, customized topologies and design techniques will be created to construct a flexible receiver front-end. RadioRTML will be prototyped on a System-on-Chip (SoC)-based software-defined radio (SDR) connected to a custom-designed printed circuit board for the RF front-end chip. To thoroughly train and test the RadioRTML algorithms, large-scale data collection will be performed utilizing Arena (a 64-antenna 24-SDR system located at Northeastern University), Colosseum (the world’s largest network emulator), and the NSF POWDER testbed.
This award reflects NSF’s statutory mission and has been deemed worthy of support through evaluation using the Foundation’s intellectual merit and broader impacts review criteria.
NSF Abstract: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2218845